The present invention relates to a data processing system having a main memory and a high speed memory and, more particularly, to an improved memory access management mechanism for controlling data transfer therebetween.
In the field of data processing, sophisticated high speed computers often incorporate large memories or data storage devices. While the speed of the engines or processors within such computer systems has consistently increased over the years, so too have computer applications continued to demand ever greater speeds.
Among the many variables to be considered in an attempt to increase the performance of data processing systems, two considerations are the speed of the system processor and the speed with which data can be transferred between the main storage and the processor. In general, when two or more logic devices are incorporated in a computer system, one of the devices operates at a slower rate of speed than do the remaining devices. Overall system performance is of course dependent upon the speed of the slowest logical device.
The speed of a memory device is inversely proportional to the time required to access data stored therein. As sophisticated computer systems develop, memory storage capacity often increases. Although the operating speed of the smallest components may increase, overall system performance may, in fact, degenerate when memory capacity is extremely large.
Historically, it was common for a processor to communicate with main storage by means of individual connections thereto. The great increase in processing power provided by modern processors, however, resulted in a prodigious amount of data constantly being requested by the processor, exceeding the capacity of the main storage to transfer data to the processor at optimal rates. The size of the memory required for use also increased at a faster rate than that of processor improvement. It would have been uneconomical to continue building nonvolatile memories of ever increasing size and speed.
An approach to maximizing performance of a computer system was to develop a temporary memory storage mechanism called a cache. The cache is a relatively high speed memory that tends to be more expensive than conventional data storage devices.
The cache is a limited storage capacity memory that is usually local to the processor and that contains a time-varying subset of the contents of main storage. This subset of data stored in the cache is that data that was recently used by the processor.
The purpose of a cache memory is to reduce cost of a system while minimally affecting the average effective access time for a memory reference. A very high proportion of memory reads can be satisfied out of the high speed cache.
The cache contains a relatively small high speed buffer and control logic situated between two logical devices, such as a processor and main storage. The cache matches the high speed of one of the devices (the processor) to the relatively low speed of the other device (the main storage).
The data most often used is temporarily stored in the high speed buffer. The most recent information requested by one logical device from another logical device is stored in the cache memory simultaneously with its transfer to the first device. Subsequent requests for such information result in the transfer of data directly from the cache to the first device without need for accessing the second device.
When a processor, for example, requests data, a cache first searches its buffer. If the data is stored in the cache, a so-called hit occurs. The data is returned in one or two cycles. Often, of course, the data sought is not stored in the cache. Consequently, a so-called miss occurs and the cache must retrieve the data from main storage.
Caches derive their performance from the principle of locality. According to this principle, over short periods of time processor memory references tend to be clustered in both time and space. Data that will be in use in the near future is likely to be currently in use. Similarly, data that will be in use in the near future is located near data currently in use. The degree to which systems exhibit locality determines the benefits of the cache. A cache can contain a small fraction of the data stored in main storage, yet still have hit rates that are extremely high under normal system loads.
A main storage line fetch occurs when the cache accesses data from main storage. A line castout occurs when a convenient block of data, called a line or cache line, is returned to main storage from the cache after modification to make room for a new line of data. The line of data is the unit which is moved between the cache and main storage and is typically 4 to 16 times longer than the width of the bus between the cache and main storage. This incompatibility results in multiple transfers of data between memory and cache to complete a data transfer operation.
The loading of the cache device is sometimes called inpaging. Inpaging of data from main storage to the cache may take an appreciable amount of time, depending upon the amount of data that is transferred. Often particular data within a line which the processor requests is fetched from main storage first and passed to the processor so that it can resume instruction processing. The remainder of the line is inpaged into the cache immediately afterward. If, during the inpaging operation, a processor requires access to data in the cache, conventionally the processor has been required to wait until the line transfer operation from main storage to the cache was completed.
U.S. Pat. No. 4,317,168 issued to Messina et al discloses a cache organization that enables cache functions to overlap. The main storage has two lines: data bus-out and data bus-in, each transferring a double word in one cycle. Both buses may transfer respective double words in opposite directions in the same cycle. Moreover, the cache has a quadword write register and a quadword read register, a quadword meaning two double words on a quadword address boundary. During a line fetch of sixteen double words, the first double word or the pair of double words is loaded into the quadword write register. Thereafter, during the line fetch the even and odd double words are formed into quadwords as received from the bus-out and the quadwords are written into the cache on alternate cycles. If a line castout is required from the same or a different location in the cache, the castout can proceed during the alternate non-write cycles of any line fetch. Any cache bypass to the processor during the line fetch can overlap the line fetch and the line castout. Although processor accesses are permitted in the aforementioned system, they receive lower priority than do memory transfers.
U.S. Pat. No. 4,169,284 issued to Hogan et al teaches concurrent access to a cache by main storage and a processor by means of a cache control which provides two cache access timing cycles during each processor storage request cycle. No alternatively accessible modules, buffering, delay or interruption is provided for main storage line transfers to the cache.
U.S. Pat. No. 4,371,929 issued to Brann et al teaches a controllable cache store interface to a shared disk memory employing a plurality of storage partitions whose access is interleaved in a time domain multiplexed manner. A common bus is provided with the shared disk to enable high speed sharing of the disk storage by all processors in a multiprocessor system. The communication between each processor and its corresponding cache memory partition can be overlapped with one another and with accesses between the cache memory and the commonly shared disk memory. Interleaving of transfers within full disk block transfers, however, is not permissible. Thus, processor access to the cache memory is halted until data is transferred from the cache to the disk drives.
It would be advantageous to provide a system for improving performance of a high speed computer.
It would also be advantageous to provide a system for efficient data management between a cache and a main storage in such a high speed computer system.
It would further be advantageous to provide a system for interrupting cache operations when a processor requests access to the data stored therein.
Moreover, it would be advantageous to allow a processor to have highest access to the cache, even when data transfer operations are occurring between the cache and main storage.
It would also be advantageous to provide a system for buffering data from main storage to the cache so that data can be loaded continuously into the cache unless the processor requests access to the data.